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oki semiconductor fedl9226-01 issue date: dec. 11, 2002 ml9226 32-bit duplex/triplex vfd controller/driver with digi tal dimming, adc and keyscan 1/26 general description the ml9226 is a full cmos controller/driver for duplex or triplex vacuum fluorescent display tube. it conststs of 32-segment driver outputs and 3-grid pre-driver outputs, so that it can drive directly up to 96-segment vfd. ml9226 features a digital dimming function, a 8-ch adc, a 5 5 keyscan circuit and an encoder type switch interface. ml9226 provides an interface with a microcontroller onl y by four signal lines: data i/o, clock, cs. features ? supply voltage (v disp ) : 8 to 18.5v (built-in 5v regulator for logic) ? duplex/triplex selectable ? applicable vfd tube : 2 grids 32 anodes vfd tube : 3 grids 32 anodes vfd tube ? 32-segment driver outputs : i oh = ?5 ma at v oh = v disp ? 0.8 v (seg1 to 22) i oh = ?10 ma at v oh = v disp ? 0.8 v (seg23 to 32) i ol = 500 ua at v ol = 2.0 v (seg1 to 32) ? 3-grid pre-driver outputs : i oh = ? 5.0 ma at v oh = v disp ? 0.8v i ol = 10 ma at v ol = 2.0v ? built-in digital dimming circuit (10-bit resolution) ? built-in 8-ch a/d converter ? built-in 5 5 keyscan circuit ? 3 interface circuits for an encoder type rotary switch ? built-in oscillation circuit (external r and c) ? built-in power-on-reset circuit ? package: 80-pin plastic qfp (qfp80-p-1420-0.80-bk) ( ML9226GA)
fedl9226-01 oki semiconductor ml9226 2/26 block diagram timing generator dim out sync out1 sync out2 dup/ tr i osc control out1-32 32bit shift register in1-10 dimming latch out1-10 10bit digital dimming por cs cloc k data i/o out1-3 3bit shift register por por por 4h out1-32 segment latch 3 in1-32 0h 3h po r out1-32 segment latch 2 in1-32 0h 2h por out1-32 segment latch 1 in1-32 0h 1h por mode select in1-3 por 0h 7h 5 v regulator & power on reset v cc (5 v) l-gnd por out1-32 96 to 32 segment control in1-32 in1-32 32 segment driver d-gnd v disp 3 grid pre driver g rid2 g rid3 g rid1 seg32 seg1 vreg(5 v) 5 5 key scan and encoder switch interface int 8ch, 8bit a/d converter osc0 ch1 ch8 c ol1 c ol5 row1 row5 a1 b1 5h 6h 7h a2 b2 a3 b3 in1-32
fedl9226-01 oki semiconductor ml9226 3/26 pin configuration (top view) seg21 seg25 seg26 seg27 80 79 78 77 76 75 74 73 72 71 70 69 68 nc seg22 seg23 nc seg24 seg20 seg19 seg18 nc l-gnd 25 a1 26 b1 27 int 28 dup/ tr i 29 v cc 30 osc0 31 32 33 34 35 36 37 data i/o cloc k cs sync out2 sync out1 dim out 61 62 63 64 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 seg13 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg12 seg1 ch8 ch7 ch6 ch5 v disp seg14 15 16 17 18 19 4 3 2 1 5 6 7 8 9 10 11 12 13 14 row5 col 1 col 2 col 3 col 4 v disp seg28 seg29 seg30 seg31 seg32 grid 1 grid 2 grid 3 d-gnd row1 row2 row3 row4 20 21 22 23 24 38 39 40 45 44 43 42 41 ch4 ch3 ch2 ch1 vreg 67 66 65 seg17 seg16 seg15 nc nc nc col 5 a3 b3 a2 b2 nc: no connection (open) 80-pin plastic qfp
fedl9226-01 oki semiconductor ml9226 4/26 pin descriptions pin symbol type description 1, 64 v disp ? power supply pins. pin1 and pin64 should be connected externally. 10 d-gnd ? 33 l-gnd ? d-gnd is ground pin for the vfd driver circuit. l-gnd is ground pin for the logic circuit. pins 10 and 33 should be connected externally. 30 v cc o 5 v output pin for internal logi c portion and external logic circuit. 41 v reg o reference voltage (5 v) out put pin for a/d converter. 50 to 63, 65 to 67, 69 to 71, 73, 74 seg1 to 22 o segment (anode) signal output pins for a vfd tube. these pins can be directly connected to the vfd tube. external circuit is not required. i oh ?5 ma 75, 76, 78 to 80, 2 to 6 seg23 to 32 o segment (anode) signal output pins for a vfd tube. these pins can be directly connected to the vfd tube. external circuit is not required. i oh ?10 ma 7, 8, 9 grid1 to 3 o inverted grid signal output pins. for pre-driver, the external circuit is requiend. i ol 10 ma 36 cs i chip select input pin. data input/output operation is valid w hen this pin is set at a high level. 35 clock i serial clock input pin. data is input and/or output through t he data i/o pin at the rising edge of the serial clock. 34 data i/o i/o serial data input/output pin. data is input to/comes out from the shift register at the rising edge of the serial clock. 27 int o interrupt signal output to microcontrolle r. when any key of key matrix is pressed or released, key scanning is st arted. after the completion of the one cycle, this pin goes to high level and keeps the high level until keyscan stop mode is selected. 29 dup/ tri i duplex/triplex operation select input pin. duplex (1/2 duty) operation is selected when this pin is set at a v cc level. triplex (1/3 duty) operation is selected when this pin is set at a gnd level. 42 to 49 ch1 to 8 i analog voltage input pin for the 8-bit a/d converter. 21 to 26 a1 to a3 b1 to b3 i input pin for the encoder type rotary switch. the phase of an an/bn input is detected. 16 to 20 col1 to 5 i return inputs from the key matrix. these pins are active low. when key matrix are in the inactive sate, these pins are at high level through the inte rnal pull-up resistors. all the inputs do not have the cahttering absorpt ion function for the keyscans. 11 to 15 row1 to 5 o key switch scanning outputs. normally low level is output through t hese pin. when any switch of key matrix is depressed or released, key scanning is started and is continued until keyscan stop mode is select ed. when keyscan stop mode is selected, all outputs of row1 to 5 go back to low level.
fedl9226-01 oki semiconductor ml9226 5/26 pin symbol type description 40 dim out o dimming pulse output. connect this pin to the slave side dim in pin. 38, 39 sync out 1, 2 o synchronous signal input. connect these pins to the sync in1 and sync in2 pins of a slave side. 31 osc0 i/o rc oscillator connecting pins. oscillation frequency depends on display tubes to be used. for details refer to electrical characteristics. v cc osc0 r co 28,32, 37,68, 72,77 nc - open pins.
fedl9226-01 oki semiconductor ml9226 6/26 absolute maximum ratings parameter symbol condition rating unit supply voltage v disp ? ?0.3 to +20 v input voltage v in ? ?0.3 to +6.0 v power dissipation p d ta = 85c qfp80-p-1420-0.80-bk 263 mw storage temperature t stg ? ?55 to +150 c i o1 seg1 to 22 ?10.0 to +2.0 ma i o2 seg23 to 32 ?20.0 to +2.0 ma i o3 grid1 to 3 ?10.0 to +20.0 ma output current i o4 dim out, sync out1, sync out2 ?2.0 to +2.0 ma recommended operating conditions parameter symbol condition min. typ. max. unit driver supply voltage v disp ? 8.0 13.0 18.5 v high level input voltage v ih all inputs except osc0 3.8 ? ? v low level input voltage v il all inputs except osc0 ? ? 0.8 v clock frequency f c ? ? ? 2.0 mhz oscillation frequency f osc r = 10 k ? 5%, co = 27 pf 5% 2.2 3.3 4.4 mhz 1/3 duty 179 269 358 hz frame frequency f fr r = 10 k ? 5% co = 27 pf 5% 1/2 duty 268 403 538 hz operating temperature t op ? ?40 ? +85 c
fedl9226-01 oki semiconductor ml9226 7/26 electrical characteristics dc characteristics (ta = ?40 to +85c, v disp = 8.0 to 18.5 v) parameter symbol applied pin condition min. max. unit high level input voltage v ih *1) ? 3.8 ? v low level input voltage v il *1) ? ? 0.8 v i ih1 *2) v ih = 3.8 v ?5.0 +5.0 a high level input current i ih2 *3) v ih = 3.8 v ?70 ?5.0 a i il1 *2) v il = 0.0 v ?5.0 +5.0 a low level input current i il2 *3) v il = 0.0 v ?160 ?10 a v oh1 seg1 to 22 i oh1 = ?5 ma v disp ? 0.8 ? v v oh2 seg23 to 32 i oh2 = ?10 ma v disp ? 0.8 ? v v oh3 grid1 to 3 i oh3 = ?5 ma v disp ? 0.8 ? v i oh4 = ?200 a 4.0 ? v high level output voltage v oh4 *4) v disp = 9.5 v output open 4.5 ? v v ol1 seg1 to 22 i ol1 = 500 a ? 2.0 v v ol2 seg23 to 32 i ol2 = 500 a ? 2.0 v v ol3 grid1 to 3 i ol3 = 10 ma ? 2.0 v low level output voltage v ol4 *5) v disp = 9.5 v i ol4 = 300 a ? 0.4 v supply current i disp v disp r = 10 k ? 5%, co = 27 pf 5% no load ? 10 ma supply voltage for logic v l v cc c = 0.01 f 10%, i o = 0 to ?10 ma 4.5 5.5 v *1) cs, clock, data i/o dup/ tri , a1 to a3, b1 to b3, col1 to 5 *2) cs, clock, data i/o dup/ tri , a1 to a3, b1 to b3 *3) col1 to 5 *4) data i/o, int, dim out, sync out1, sync out2 *5) data i/o, int, dim out, sync out1, sync out2, row1 to 5
fedl9226-01 oki semiconductor ml9226 8/26 ac characteristics (ta = ?40 to +85c, v disp = 8.0 to 18.5 v) parameter symbol condition min. max. unit clock frequency f c ? ? 2.0 mhz clock pulse width t cw ? 200 ? ns data setup time t ds ? 200 ? ns data hold time t dh ? 200 ? ns cs off time t csl r = 10 k ? 5%, co = 27 pf 5% 20 ? s cs setup time (cs-clock) t css ? 200 ? ns cs hold time (clock-cs) t csh ? 200 ? ns data output delay time (clock-data i/o) t pd ? ? 1.0 s t r t r = 20% to 80% ? 2.0 s output slew rate time t f c l = 100 pf t f = 80% to 20% ? 2.0 s v disp rise time t prz mounted in a unit ? 100 s v disp off time t pof mounted in a unit, v disp = 0.0 v 5.0 ? ms cs wait time t rsoff ? 400 ? s
fedl9226-01 oki semiconductor ml9226 9/26 timing diagram data input timing ? 3.8 v ? 0.8 v ? 3.8 v ? 0.8 v ? 3.8 v ? 0.8 v cs clock data i/o (input) t ds t dh t css 1/f c t cw t cw t csh t csl valid valid valid valid data output timing ?3.8 v ? 0.8 v ? 3.8 v ? 0.8 v ? 3.8 v ? 0.8 v cs clock data i/o (output) t pd t css t csh reset timing t pof t prz v disp cs t rsoff ? 0.8v disp ? 0.0 v ?3.8 v ? 0.0 v driver output timing ?0.8v disp ?0.2v disp seg1-32, grid1-3 t r t f
fedl9226-01 oki semiconductor ml9226 10/26 a/d converter characteristics (ta = ?40 to +85c, v disp = 8.0 to 18.5 v) parameter condition min. typ. max. unit reference voltage (v reg ) ? 4.5 5.0 5.5 v output current ? ? ? ?10 ma input voltage range ? gnd ? v reg v conversion time/channel r = 10 k ? 5%, c2 = 27 pf 5% 256 310 394 s resolution ? ? 8 bit linearity error ? ? 2.0 lsb differentiation linearity error ? ? 2.0 lsb zero scale error ? ? +2.0 lsb full-scale error ? ? -2.0 lsb terminological definition resolution the minimum input analog value which can be recognized. it can decompose into 2 8 = 256,(v rh -v rl )/256,in 8 bits. linearity error the deviation between the ideal conver sion characteristic as a 8-bit a /d converter and the actual conversion characteristic is said. (therefore, a quantization error is not included.) the ideal conversion characteristic means t he step which divided the voltage between v rh to v rl into 256 division into equal parts . differentiation linearity error the smoothness of the conversion ch aracteristic is shown, and ideally, the width of the anal og input voltage corresponding to change for 1 bit of digital outputs is 1lsb= (v rh -v rl )/256, and says the deviation of this ideal bit size and the bit size in the arbitrar y points of the conversion range. zero scale error digital output "000h" to "001h" c hanges, and the deviation of the ideal conversion characteristic of a point and the actual conversion characteristic is said. full scale error digital output "0feh" to "0ffh" changes, and the deviation of the ideal conversion characteristic of a point and the actual conversion characteristic is said.
fedl9226-01 oki semiconductor ml9226 11/26 keyscan characteristics (ta = ?40 to +85c, v disp = 8.0 to 18.5 v) parameter condition min. typ. max. unit keyscan cycle time r = 10 k ? 5%, co = 27 pf 5% 160 194 246 s keyscan pulse width r = 10 k ? 5%, co = 27 pf 5% 32 39 49 s rotary switch characteristic (ta = ?40 to +85c, v disp = 8.0 to 18.5 v) parameter sign condition min. typ. max. unit phase input time t abw phase input fixed time t abh r = 10 k ? 5%, c o = 27 pf 5% 950 ? ? s rotary switch input timing a b keyscan timing row1 row5 row2 row3 row4 keyscan cycle time keyscan pulse width t abw t abw t abw t abw t abh t abh
fedl9226-01 oki semiconductor ml9226 12/26 output timing (duplex op eration) *1 bit time = 4/f osc solid line : the dimming data is 1016/1024 dotted line : the dimming data is 64/1024 output timing (triplex operation) *1 bit time = 4/f osc solid line : the dimming data is 1016/1024 dotted line : the dimming data is 64/1024 1016 bit times 1016 bit times 1016 bit times grid1 vdisp d-gnd grid2 vdisp d-gnd grid3 seg1-32 vdisp d-gnd dim out 5v l-gnd sync out1 5v l-gnd sync out2 5v l-gnd vdisp d-gnd 2048 bit times(1 display cycle) 8 bit times 8 bit times 8 bit times 64 bit times 64 bit times 64 bit times 1016 bit times 1016 bit times 1016 bit times grid1 vdisp d-gnd grid2 vdisp d-gnd grid3 seg1-32 vdisp d-gnd dim out 5v l-gnd sync out1 5v l-gnd sync out2 5v l-gnd vdisp d-gnd 3072 bit times(1 display cycle) 8 bit times 8 bit times 8 bit times 64 bit times 64 bit times 64 bit times
fedl9226-01 oki semiconductor ml9226 13/26 functional description power-on reset when power is turned on, ml9226 is initialized by the internal power-on reset circuit. the status of the internal circuit after initialization is as follows: ? the contents of the shift regist ers and latches are set to ?0?. ? the digital dimming duty cycle is set to ?0?. ? all segment outputs are set to low level. ? grid1 outputs are set to low level. ? grid2 to 3 outputs are set to high level. ? all the row outputs are set to low level. ? int output is set to low level. mode data ml9226 has the seven function modes. the function mode is selected by the mode data (m0 to m2). the relation between function mode and mode data (m0 to m2) is as follows: function data function mode operating mode m0 m1 m2 0 segment data for grid1-3 input 0 0 0 1 segment data for grid1 input 1 0 0 2 segment data for grid2 input 0 1 0 3 segment data for grid3 input 1 1 0 4 digital dimming data input 0 0 1 5 keyscan stop 1 0 1 6 switch data output 0 1 1 7 a/d data output 1 1 1 data input and output data input and output through the data i/o pin is valid only when the cs pin is set at a high level. the input data to data i/o pin is shifted into the shift regi ster at the rising edge of th e serial clock. the data is automatically loaded to the latches when the cs pin is set at a low level. 10-bit dimming data (d1 to d10) and 32-bit segment data (s1 to s32) are used for inputting of dimming data and display data. to transfer these two data, the mode data (m0 to m2) must be sent after each of these data succeddingly. the output data from the data i/o pin is output from the shift register at the rising edge of the serial clock. ml9226 outputs 64-bit (8 ch 8 bits) a/d data (a11 to a88) and 37-bit key data (s11 to s55, r1, q11 to q13, r2, q21 to q23, r3 and q31 to q33). to r eceive these data, the mode data (m0 to m2) mast be sent first and then cs must be set once to low level and set again to high level. then inputting serial clocks, these data are output from the data i/o pin. when the cs pin is set at a low level, the data i/o pin returns to an input pin. to stop the keyscan, the only mode data (m0 to m2) must be sent. after the mode data transfer, the key scanning is stopped immediately.
fedl9226-01 oki semiconductor ml9226 14/26 segment data input [function mode: 0 to 3] ? ml9226 receives the segment data when function mode 0 to 3 are selected. ? the same segment data is transferred to the 3 segment data latch correspond to grid1 to 3 at the same time when the function mode 0 is selected. ? the segment data is transferred to only one segment data latch that is selected by mode data, when the function mode is 1, 2 or 3 is selected. ? segment output (seg1 to 32) becomes high level when the segment data (s1 to 32) is high level. [data format] input data : 35 bits segment data : 32 bits mode data : 3 bits 1 s1 2 s2 3 s3 4 s4 29 s29 30 s30 31 s31 32 s32 33 m0 34 m1 35 m2 bit input data segment data (32 bits) mode data (3 bits) lsb msb [bit correspondence between segment output and segment data] seg n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 segment data s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 seg n 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 segment data s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 s32
fedl9226-01 oki semiconductor ml9226 15/26 digital dimming data i nput [function mode: 4] ? ml9226 receives the digital dimming data when function mode 4 is selected. ? the output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. ? the 10-bit digital dimming data is input from lsb. [data format] input data : 13 bits digital dimming data : 10 bits mode data : 3 bits 1 d1 2 d2 3 d3 4 d4 7 d7 8 d8 9 d9 10 d10 11 m0 12 m1 13 m2 bit input data digital dimming data (10 bits) 5 d5 6 d6 lsb msb mode data (3 bits) (lsb) dimming data (msb) d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 duty cycle 0 0 0 0 0 0 0 0 0 0 0/1024 1 0 0 0 0 0 0 0 0 0 1/1024 1 1 1 0 1 1 1 1 1 1 1015/1024 0 0 0 1 1 1 1 1 1 1 1016/1024 1 0 0 1 1 1 1 1 1 1 1016/1024 1 1 1 1 1 1 1 1 1 1 1016/1024 keyscan stop [function mode: 5] ? ml9226 stops a key scanning when function mode 5 are selected. ? to select this mode, the only mode data (m0 to m2) is needed. ? the actual time lag range between receipt of the keys can stop command and the ceasing of scanning is 2.4 s to 3.6 s [input data format] input data : 3 bits mode data : 3 bits bit 28 29 30 input data m0 m1 m2 mode data (3 bits)
fedl9226-01 oki semiconductor ml9226 16/26 switch data output [function mode: 6] ? ml9226 output the switch data when function mode 6 is selected. ? to select this mode, the only mode data (m0 to m2) is needed. ? when ml9226 recieves this mode, the data i/o pin is changed to an output pin. ? 37-bit switch data come out from the data i/o pin synchronizing with the rise edge of the clock. ? when the cs pin is set at the low level, the data i/o pin returns to an input pin. ? r1, r2, r3 = 0, implies right rotation of the knob (clockwise) ? r1, r2, r3 = 1, implies left rotation of the knob (counter clockwise) ? contact count bits are q11 (lsb) to q13 (msb), q21 (lsb) to q23 (msb) and q31 (lsb) to q33 (msb) [input data format] input data : 3 bits mode data : 3 bits bit 28 29 30 input data m0 m1 m2 mode data (3 bits) [output data format] output data : 37 bits 5 5 push swithc data : 25 bits encoder switch data : 12 bits bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 output data s11 s12 s13 s14 s15 s21 s22 s23 s24 s25 s31 s32 s33 s34 s35 s41 s42 s43 s44 s45 s51 s52 s53 s54 s55 bit 26 27 28 29 30 31 32 33 34 35 36 37 output data r1 q11 q12 q13 r2 q21 q22 q23 r3 q31 q32 q33 sij: i = row1 to 5, j = col1 to 5 sij = 1: switch on sij = 0: switch off [5x5 push switch] row1 row2 row3 row4 row5 c ol1 c ol2 c ol3 c ol4 c ol5 =
fedl9226-01 oki semiconductor ml9226 17/26 keyscan keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by scanning signal. then, keyscanning is continued until the keyscan stop mode is sent from a microcomputer. the int pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the int pin can be used as an interrupt signal. [keyscan timing] 1 cycle int row 5 row 4 row 3 row 2 row 1 depress/release keyscan stop mode is selected. note: keyscanning cannot be stopped by sel ecting the keyscan stop mode only once if: - keyscanning is started after depression or release of any key is detected, and then - a key is depressed or released again before the keyscan stop mode is selected. to stop keyscanning, it is required to select the keyscan stop mode once again. depress depress release keyscan keyscan int cs mode5 mode5 mode5 mode5 : keyscan stop
fedl9226-01 oki semiconductor ml9226 18/26 a/d data output [function mode: 7] ? ml9226 output the a/d data when function mode 7 is selected. ? to select this mode, the only mode data (m0 to m2) is needed. ? when ml9226 recieves this mode, the data i/o pin is changed to an output pin. ? 64-bit a/d data come out from the data i/o pin synchronizeing with the rise edge of the clock. ? when the cs pin is set at the low level, the data i/o pin returns to an input pin. [input data format] input data : 3 bits mode data : 3 bits bit 28 29 30 input data m0 m1 m2 mode data (3 bits) [output data format] output data : 64 bits a/d data : 64 bits bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 output data a11 (lsb) a12 a13 a14 a15 a16 a17 a18 (msb) a21 (lsb) a22 a23 a24 a25 a26 a27 a28 (msb) a/d ch1 ch2 bit 17181920212223242526272829303132 output data a31 (lsb) a32 a33 a34 a35 a36 a37 a38 (msb) a41 (lsb) a42 a43 a44 a45 a46 a47 a48 (msb) a/d ch3 ch4 bit 33343536373839404142434445464748 output data a51 (lsb) a52 a53 a54 a55 a56 a57 a58 (msb) a61 (lsb) a62 a63 a64 a65 a66 a67 a68 (msb) a/d ch5 ch6 bit 49505152535455565758596061626364 output data a71 (lsb) a72 a73 a74 a75 a76 a77 a78 (msb) a81 (lsb) a82 a83 a84 a85 a86 a87 a88 (msb) a/d ch7 ch8
fedl9226-01 oki semiconductor ml9226 19/26 the rotary encoder switch function. as figure 1 shows, the rotary encoder switch circuit is co nsisted of phase detection, interrupt generation, up/down counter, direction latch and parallel-in serial-out shift register. phase detection up down b q3 q2 q1 a up/down counter p-in/s-out shift registor r1 direction latch interrupt generation for int output data fig.1 the rotary encoder switch circuit 1) phase detection 1-1) clockwise when signal a and b input as fig. 2, the phase detection circuit outputs up signal after the chattering absorption period. at this time, the output int also goes to high level, so this signal can be used as an interrupt. the int stays high level until the key scan stop mode is selected. up (internal) b a int chattering absorption time fig.2 the input and output timing in case of clockwise.
fedl9226-01 oki semiconductor ml9226 20/26 1-2) counter clockwise when signal a and b input as fig. 3, the phase detection circuit outputs down signal after the chattering absorption period. at this time, the output int also goes to high level. the int stays high level until the key scan stop mode is selected. down (internal) b a int chattering absorption time fig.3 the input and output timing in case of counter clockwise. 2) up/down counter when the up/down counter is input up, it counts up and when it is input down, it counts down. but if overcounte of ?111? occurs the up/down counter stays ?111?. b q1, q2, q3 a 100 010 110 001 101 011 111 111 fig.4 3) direction latch when the direction latch is input down the output r goes ?1?. but if the up pulse is input and the counts value change to plus value, the output r goes to ?0?. b q1, q2, q3 a 010 100 100 100 000 010 r1 fig.5
fedl9226-01 oki semiconductor ml9226 21/26 4) p-in/s-out shift resistor when the key scan stop mode is selected and sc goes l, int signal goes ?l?. cs data i/o clock int signal goes ?l?. int c2 c1 c4 c3 c1 c5 c3 c2 c5 c4 row1 row2 c2 c1 c4 c3 r1 c5 q11 q12 q13 r2 q21 q22 q23 r3 q31 q32 q33 row5 rotary fig.6
fedl9226-01 oki semiconductor ml9226 22/26 application circuits 1. circuit for the duplex vfd tube with 128 segments (2 grid 64 anode) ml9226 (master) v disp v cc vreg dup/ tri sync out 2 sync out 1 dim out seg1 ml9213 (slave) v disp v dd l-gnd sync out 2 sync out 1 dim out grid 1 grid 2 grid 3 seg1 seg56 duplex vfd tube s62 s63 s64 s1 s2 s3 g1 g2 microcontroller v disp m/ s gnd dup/ tri e f ch1 to 8 row1 to 5 col1 to 5 5 5 key matrix gnd seg32 grid 1 grid 2 grid 3 l-gnd cs data i/o clock v cc osc0 gnd gnd gnd sync in 2 sync in 1 dim in cs data in clock osc 1 osc 0
fedl9226-01 oki semiconductor ml9226 23/26 2. circuit for the triplex vfd tube with 192 segments (3 grid 64 anode) ml9226 (master) ml9213 (slave) v disp v dd l-gnd seg1 triplex vfd tube s62 s63 s64 microcontroller v disp gnd e f ch1 to 8 row1 to 5 col1 to 5 5 5 key matrix vreg dup/ tri s3 s2 g1 g2 g3 seg56 grid 1 grid 2 grid 3 gnd sync out 2 sync out 1 dim out v disp dup/ tri m/ s v cc l-gnd cs data i/o clock v cc osc0 gnd gnd gnd s1 sync in 2 sync in 1 dim in cs data in clock osc 1 osc 0 sync out 2 sync out 1 dim out seg1 seg32 grid 2 grid 3 grid 1
fedl9226-01 oki semiconductor ml9226 24/26 package dimensions qfp80-p-1420-0.80-bk mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 1.27 typ. 5 rev. no./last revised 4/nov. 28, 1996 notes for mounting the surface mount type package the surface mount type packages ar e very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform refl ow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ( unit: mm )
fedl9226-01 oki semiconductor ml9226 25/26 revision history page document no. date previous edition current edition description fedl9226-01 dec. 11, 2002 ? ? preliminary edition 1
fedl9226-01 oki semiconductor ml9226 26/26 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circu it, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improp er installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third part y?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communicati on equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifica lly authorized by oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications includ e, but are not limited to, traffic and auto motive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2002 oki electric industry co., ltd.

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